posted in Technology
Japan tried to build an operating system for the entire world, then the US government intervened
www.xda-developers.com/japan-tried-build-operating-system-entire-world-us-government-intervened/
Something similar happened to Slovene Iskra Triglav computer which was quite advanced for the time (capable of running three different CPUs) but then caught in between US-Soviet cold war/embargo while trying to sell them to Soviet Union.
Three CPUs with different architectures on one device sounds crazy. That’s amazing.
PS3 comes to mind
Though in embedded, thats fairly normal.
I’ve got a $1 linux embedded SoC that has a 64 bit riscv core, a 32 bit riscv core for running realtime stuff and a low power embedded 6502 on it too because why not.
Yeah, RP2350 in Raspberry Pi Pico 2 also has 2 ARM cores and 2 RISC-V cores.
Which reminds me, I purchased one a month ago to play around with as it has good documentation, yet I haven’t used it once so far.
Its actually not seperate cores, they’re RISCV or ARM, based on a switch. MilkV does that too with one of its chips. They’re mostly the same architecturally, theres something like 10% that gets enabled/disabled with each ISA selection.
Replying to @greyscale@lemmy.grey.ooo
But you can still run both at once. RP2350 datasheet
From section 3.9 Arm/RISC-V architecture switching:
There are two processor sockets on RP2350, referred to as core 0 and core 1 throughout this document. Each socket can be occupied either by a Cortex-M33 processor (implementing the Armv8-M Main architecture, plus extensions) or by a Hazard3 processor (implementing the RV32IMAC architecture, plus extensions).
From section 3.9.2. Mixed architecture combinations:
The
ARCHSELregister has one bit for each processor socket, so it is possible to request mixed combinations of Arm and RISC-V processors: either Arm core 0 and RISC-V core 1, or RISC-V core 0 and Arm core 1.Practical applications for this are limited, since this requires two separate program images. The two cores interoperate normally, including shared exclusives via the global monitor: a shared variable can be safely, concurrently accessed by an Arm processor performing
ldrex,strexinstructions and a RISC-V processor performingamoadd.winstructions, for example
My point it isn’t 2x arm and 2x riscv. They recycle most of the silicon used.